1. Field of the Invention
The present invention relates to data transmission, and more particularly to serializing and sending, bit by bit, data where the data word boundary is determined in order to properly receive and de-serialize the data.
2. Background Information
FIG. 1 illustrates a known serializer in a block schematic form. A parallel data word 10 is loaded into a buffer register 12 with a word clock 14. The word clock 14 is also fed to a phase locked loop (PLL) or a delay locked loop (DLL) 16, hereinafter PLL will be used to refer to both the PLL and DLL. The PLL generates a bit clock 18 that loads the shift register 20 and subsequently shifts out the data in the shift register 20 serially bit by bit through a cable or transmission line driver 22. The bit clock 18 that shifts the data out bit by bit stays synchronized to the bit positions within the word by the PLL. Along with the serial bits from driver 22 a word clock 24 is output via driver 26. The receiver will be able to distinguish the beginning and ending of the serial data stream by referencing the bit stream via the word clock.
FIG. 2 shows a receiver circuit that de-serializes the bits to form words. The serial data 30 is input to a shift register 32. The word clock 34 is input to a PLL 36 that generates a bit clock 38 that is synchronized to the bit location in a word by the PLL. With this synchronization, the bit clock 38 properly loads the bit stream into the shift register 32. When the word has been received by the shift register 32 (as determined from the word clock), the PLL outputs a clock 40 that loads the parallel data in the shift register 32 into a buffer register 42. The word data 44 is in parallel form ready for use in the receiving system.
FIGS. 1 and 2 contain a buffer register that holds the word to be sent or the word just received. The buffer allows nearly the entire time for a word to be sent or received before the next word is loaded. The logic and the timing to accomplish these tasks are well known. However, the buffer registers are not required, and if not used then the word to be sent and the word received must be loaded during a bit time. Again such designs are well known in the art.
FIG. 3 shows a complete bidirectional system using the serializers as in FIG. 1 and deserializers as in FIG. 2. Note that there are eight data lines and a single clock into each serializer and out from each deserializer. The data and clock lines between the serializer and the deserializer are typically differential signals each using two conductors.
The serializer/deserializer of FIG. 3 each contain a PLL that are common in such devices, but PLL's consume significant power, are complex, require long locking times, and occupy considerable chip real estate. It would be advantageous to dispense with PLL's.
FIG. 4 is a timing diagram that shows a generic timing chart that illustrates the serial sending of a framed ten bit word. A word clock 60 is fed to a PLL that generates a synchronous bit clock 62, the word clock 60 must occur often enough for the PLL to remain locked. The data bits are loaded into a shift register using a word clock edge. Then the data bits in the shift register are shifted out serially by the bit clock 62. In FIG. 4 a eight bit word is shifted out on the rising edge of the bit clock 62.
A similar operation applies to the receiving of the serial data. In this case, the word clock is received and applied to a PLL that generates a synchronous (to the word clock) bit clock that is used to load the data bits into a receiving shift register. Data bits must be stable when the clocks cause the data bits to be sent and to be received. Time delays are designed into such systems to accomplish this, as known in the art. In the case shown, the data bits are sent out synchronously where the lowest order bit of the next word is sent out directly after the most significant bit of the prior word. In other instances the data may be sent out asynchronously, typically using a start and stop bit that frames the data bits. In both the synchronous and asynchronous cases, system means must be employed, as are well known in the art, to prepare the sender and the receiver to properly send and receive the data. Also, systems are arranged to send data alternately then to receive data; while other systems can send and receive simultaneously. The former is referred to as half duplex and the latter as duplex. Again, system designers understand the limitations and requirements of such systems to properly send and receive data.
It is axiomatic that the receiving system must be able to distinguish data word boundaries from a stream of serial bits, as discussed above.
The prior art designs use PLL to provide synchronous bit clocks at both the sending and the receiving systems. However, PLL's occupy significant real estate on a die and consume considerable power and time before being locked.
In general, transferring serial data offers an advantage in that the cable running between the sending and receiving systems need only have a few signals (if differential signals, one data pair and one clock pair) carrying wires (and, of course, if single ended a return wire or wires). In contrast, sending data over cables in parallel requires line drivers for each bit in a word and a clock driver. These parallel drivers consume high power and output high currents that create significant system noise.
In applications where cables or transmission lines are not used, but where parallel data is sent between integrated circuit packages, many pins on those packages must be set aside for each bit of the parallel data. In the newer designs, using sixty-four and one hundred and twenty-eight bits, the pins available on the packages become a design limitation. Larger packages, ball grid arrays, and similar packages that provide pins over the entire bottom surface of a package address this problem. However, the problem persists. Applications that may suffer from these limitations include virtually all computing systems with complex displays, e.g. cell phones, desk-top and lap top computers, electronic games, computing systems with off-chip memory, any computing system addressing bulk memory, and electronic instrumentation, monitoring and controlling equipment.
FIGS. 5 and 6 are illustrations of buffer circuits that may use logic level translators between the various different voltages used by different logic families, for example, TTL, low level TTL, CMOS, and current mode logic families.
FIG. 5 shows bidirectional buffers 70 that drive the A(0–7) signals to the B(0–7) signals when the AtoB signal is high. The signals travel the opposite direction when the BtoA signal is high. A single bidirectional buffer circuit is shown in 70 and, in this instance of eight bits, the parallel buffers for the other seven bits are indicated by 70.′ Prior art replacement of these buffer style circuits with serializers suffers from the power dissipation and complexity of the PLL's, the need for a reference clock, the lock time of the PLL, and the chip real estate occupied. In FIGS. 5 and 6 as shown, the AtoB and BtoA signals are low true. The DIR and EN-signals control the direction. In this case, the EN- must be low to allow the DIR signal to determine the data flow direction. If EN- is high, both the BtoA and AtoB are high and the A and B signals are isolated from each other.
FIG. 6 shows a buffer-type circuit where the eight data bits A(0–7) are clocked into the D-type flops, one bit shown as 80. The CK AtoB would load A0 into the flop 81. The A0 data is output as Q flop signal and then to the B0 line when AtoB is high. Similar action occurs from sending B0 to the A0 line when BtoA is high. The circuitry for the other seven bits is indicated by 80.′
It would be advantageous to use a serializer to replace the buffers of FIGS. 5 and 6 without the disadvantages of using a PLL.
Up to the present time, serializing and de-serializing data entails using PLL's that are complex and costly of power chip space and time, as discussed above. However, serializing and de-serializing would find greater acceptance if these limitations were removed.